Delta-sigma ADCs are often used in high resolution applications because, compared to other ADC implementations, the need for complex anti-aliasing filters is reduced, differential non-linearity errors are reduced and they are more robust. By trading accuracy for speed, delta-sigma ADCs allow high performance to be achieved with high tolerance to analogue component imperfections. Delta-sigma ADCs are often seen as the best choice for low to moderate frequency, high resolution applications.
In terms of implementation, continuous time (CT) delta-sigma ADCs are often preferred over their switched capacitor (SC) counterparts due to their lower power consumption, lower need for anti-aliasing filtering and their ability to operate at higher speeds.
From the point of view of topology, single-loop delta-sigma ADCs can be realised using feed-forward, feed-back or hybrid structures.
FIG. 1 illustrates schematically the topology of a feed-forward delta-sigma ADC. The feed-forward delta-sigma ADC 10 converts an analogue signal U into a digital signal Y. The ADC 10 comprises three adders 12, 14 and 16, three integrators 18, 20 and 22, four amplifiers 24, 26, 28 and 30, a quantiser 32 and a digital to analogue converter (DAC) 34. In practice, the amplifiers 24, 26, 28, 30 are typically implemented as part of the other blocks, as are adders 12 and 14. The nature of this structure will be understood by engineers skilled in the art of ADC design and therefore will not be discussed here in depth. The adder 16 combines the outputs of the three integrators 18, 20 and 22 as scaled by the gains of their respective amplifiers 24, 26 and 28. Hence the “feed-forward” label for this ADC topology.
FIG. 2 illustrates schematically the topology for a feed-back delta-sigma ADC topology. The feed-back delta-sigma ADC 36 is arranged to convert an analogue signal U into a digital signal Y. The feed-back delta-sigma ADC 36 comprises three adders 38, 40 and 42, three integrators 44, 46 and 48, four amplifiers 50, 52, 54 and 56, a quantiser 58 and a DAC 60. The digital output Y is converted to the analogue domain by the DAC 60 and is subtracted from the inputs to each of the integrators 44, 46 and 48 with appropriate scaling being done by the amplifiers 50, 52 and 54. Hence the “feed-back” label.
FIG. 3 illustrates schematically the topology of a hybrid delta-sigma ADC. The hybrid delta-sigma ADC 62 converts an analogue signal U into a digital signal Y. The ADC 62 comprises three adders 64, 66 and 68, three integrators 70, 72 and 74, four amplifiers 76, 78, 80 and 82, a quantiser 84 and a DAC 86. In ADC 62, the output of integrator 72 is fed forward via amplifier 80 to adder 68. Thus, the hybrid delta-sigma ADC 62 includes part of the feed-forward topology of ADC 10 of FIG. 1. In ADC 62, the digital output signal Y is converted to the analogue domain by DAC 86 and is subtracted from the output signal of integrator 70. Therefore, ADC 62 includes a part of the feed-back topology of ADC 36 of FIG. 2. Hence the “hybrid” label for the ADC topology shown in FIG. 3.
As just discussed, there are common elements to the ADC topologies shown in FIGS. 1 and 3. That is to say, ADCs 10 and 62 include respective feed-forward structures 88 and 90, in which there is a chain of integrators whose outputs all feed forward into an adder. In the case of feed-forward structure 88, there are three integrators 18, 20 and 22 in the chain, whereas in feed-forward structure 90, there are just two integrators 72 and 74 in the chain.